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- W2235758889 abstract "Abstract: This chapter describes key differences of ESD protection in SOI technologies as compared to bulk. It presents active rail clamp based SOI ESD protection network and design methodology including both device and circuit level characterization data. A compact model is introduced to describe the gated diode in the ESD regime. ESD characteristics of FinFETs, FinDiodes and FDSOI devices as likely device candidates for advanced SOI technologies are studied. A response surface method to conveniently optimize ESD device sizes depending on the output buffer configuration is presented. It is demonstrated that distributed and boosted rail clamp SOI ESD networks are very compact and provide an effective ESD protection solution." @default.
- W2235758889 created "2016-06-24" @default.
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- W2235758889 date "2014-01-01" @default.
- W2235758889 modified "2023-10-14" @default.
- W2235758889 title "Protecting against electrostatic discharge (ESD) in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) manufactured using silicon-on-insulator (SOI) technology" @default.
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- W2235758889 doi "https://doi.org/10.1533/9780857099259.1.243" @default.
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