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- W2243355850 abstract "A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models." @default.
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- W2243355850 date "2009-01-01" @default.
- W2243355850 modified "2023-09-22" @default.
- W2243355850 title "LOW-POWER ADDER DESIGN FOR NANO-SCALE CMOS (SHORT PAPER)" @default.
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