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- W2247016365 abstract "D-flip flop is a sequential circuit to store a bit or information. In digital environment, circuit design is a very important parameter to require into account for creating a compact and power economical design. A high speed low power compact style could be a challenge to any or all digital circuit and from these parameters power consumption with high speed is often fascinating. the most necessary purpose of this paper is to produce, power effective model of 10T D-FF using MTCMOS technique, as a replacement low power solution for VLSI design. MTCMOS (multi threshold CMOS) is more effective circuit level technique that provides a high performance and low power design by utility of both low and high threshold voltage transistor. MTCMOS circuits reduces stand by leakage power with low delay overhead. when implementing MTCMOS technique in our desired circuit power consumption reduces from 602.9E-9 to 189.4E-12 in active mode and up to 22.28E-12 in standby mode, and therefore the static leakage power reduces from 7.85E-12 to 4.14E-13 in standby mode. the method is carried out on cadence virtuoso tool at 45nm technology. Keywords: D Flip-Flop, Total Power, Static Power, Leakage, MTCMOS." @default.
- W2247016365 created "2016-06-24" @default.
- W2247016365 creator A5016787752 @default.
- W2247016365 date "2015-06-08" @default.
- W2247016365 modified "2023-09-23" @default.
- W2247016365 title "Minimization of Power in 10T D-FF using Leakage Reduction Technique" @default.
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- W2247016365 doi "https://doi.org/10.15864/ajec.v2i2.125" @default.
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