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- W2248964955 abstract "针对GHz采样的D/A转换器(DAC)设计及系统要求, 提出了一种新型的高速同步电路.该同步电路引入高速动态比较器和触发器做低电压差分信号(LVDS)的数据接收电路, 降低了功耗, 实现简单；然后利用低抖动模拟延迟锁相环和数字相位检测电路选择准确的同步时钟信号, 提高了同步电路工作频率范围.基于SMIC 0.18μm 1.8V CMOS工艺的仿真和测试结果显示, 同步电路工作的时钟频率范围覆盖250~800MHz, 支持的数据率从500Mbit·s-1~1.6Gbit·s-1, 能用于GHz采样频率的DAC核和外部LVDS发送器接口数据的同步." @default.
- W2248964955 created "2016-06-24" @default.
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- W2248964955 date "2014-08-09" @default.
- W2248964955 modified "2023-09-24" @default.
- W2248964955 title "一种用于高速D/A转换器的1.6 Gbit·s -1 同步电路" @default.
- W2248964955 doi "https://doi.org/10.13190/j.jbupt.2014.04.015" @default.
- W2248964955 hasPublicationYear "2014" @default.
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