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- W2257115890 abstract "In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it’s performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%)." @default.
- W2257115890 created "2016-06-24" @default.
- W2257115890 creator A5022740917 @default.
- W2257115890 date "2015-01-22" @default.
- W2257115890 modified "2023-09-23" @default.
- W2257115890 title "COSA and CSA based 32 -bit unsigned multipler" @default.
- W2257115890 cites W1963182185 @default.
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- W2257115890 doi "https://doi.org/10.6084/m9.figshare.1292829.v1" @default.
- W2257115890 hasPublicationYear "2015" @default.
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