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- W2266549496 abstract "A hardware design capable of supporting high-efficiency video coding (HEVC) inverse transform (IDCT) is developed for a 32-point transform unit using a single one-dimensional (1D) transform core with two transposed memories to reduce area overhead. The proposed 1D core employs two calculation paths to obtain high throughput and is able to calculate first-dimensional (1st-D) and second-dimensional (2nd-D) transformations simultaneously along two parallel paths. The results from a practical implementation of the chip demonstrate that the proposed design presents the smallest circuit area among existing 2D transform cores." @default.
- W2266549496 created "2016-06-24" @default.
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- W2266549496 date "2015-07-01" @default.
- W2266549496 modified "2023-09-30" @default.
- W2266549496 title "Area‐efficient video transform for HEVC applications" @default.
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- W2266549496 doi "https://doi.org/10.1049/el.2015.1085" @default.
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