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- W2266873561 abstract "Verification is always a major bottleneck for implementing systems. In this paper, we show how to use an approach based on scenario in order to grasp such systems. In this context, SystemC plays a particular role since the same language enables to describe systems at various modeling levels. To reach verification besides the development flow, our approach based on scenario combines the synchronization algorithms of Model Checking with Abstract Interpretation techniques. Following the bottom-up design of a concrete example, we show how the scenarios help to qualify the implementation and to optimize QoS properties; we also describe the underlying technologies." @default.
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- W2266873561 date "2008-07-22" @default.
- W2266873561 modified "2023-09-25" @default.
- W2266873561 title "Scenarios for validating systemC descriptions" @default.
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