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- W2270130810 abstract "This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
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- W2270130810 date "2016-08-01" @default.
- W2270130810 modified "2023-10-05" @default.
- W2270130810 title "A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications" @default.
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- W2270130810 doi "https://doi.org/10.1109/tcsii.2016.2531099" @default.
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