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• W2270365466 abstract "In this paper, a new hardware reduction scheme for the interconnect BIST is proposed. The modified Pseudo Random Counting Sequence provides 100% fault coverage. A scan stage table and a scan activation table solve the multiple driver contention problem of 3state enable drivers. A simplified scan stage table significantly reduces the hardware overhead of the previous architecture without the degradation of the reliability and the test time." @default.
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• W2270365466 date "2005-10-01" @default.
• W2270365466 modified "2023-09-27" @default.
• W2270365466 title "A New Hardware Efficient Interconnect BIST" @default.
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