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• W2270401521 abstract "The fabrication of peripheral CMOS devices for DRAM memories requires specific optimization with respect to a standard logic flow, imposed by the additional constraints linked to the memory element fabrication. Several process tunings are needed to keep pace with the request for low leakage and low cost devices combined with the needs of highly performant and resilient circuits. In this article, we summarize the most significant developments achieved in recent years focusing on HKMG Gate stack, junction tuning, silicide optimization for DRAM peripheral transistors. Three different solutions with different fabrication complexity and performance for HKMG, optimized junction, and thermally stable NiPt silicide fabrication, all compatible with the DRAM requirements, are discussed." @default.
• W2270401521 created "2016-06-24" @default.
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• W2270401521 date "2016-02-01" @default.
• W2270401521 modified "2023-10-01" @default.
• W2270401521 title "Optimized material solutions for advanced DRAM peripheral transistors" @default.
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• W2270401521 doi "https://doi.org/10.1002/pssa.201532791" @default.
• W2270401521 hasPublicationYear "2016" @default.
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