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• W2271389001 abstract "As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration.." @default.
• W2271389001 created "2016-06-24" @default.
• W2271389001 creator A5075465553 @default.
• W2271389001 creator A5084114351 @default.
• W2271389001 date "2010-01-01" @default.
• W2271389001 modified "2023-09-25" @default.
• W2271389001 title "On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging" @default.
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• W2271389001 doi "https://doi.org/10.4071/isom-2010-tp5-paper1" @default.
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