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- W2275779628 abstract "In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time." @default.
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- W2275779628 date "2004-12-01" @default.
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- W2275779628 title "Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints" @default.
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