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- W2276093224 abstract "A 128-stage CMOS time delay integration (TDI) image sensor with on-chip digital accumulator was presented in this paper. By using two sets of sampling capacitors and an optimized timing, the on-chip column parallel cyclic analog-to-digital converter (ADC) in the sensor conducts the correlated double sampling, digital program gain amplifying, and A/D conversion all altogether in one ADC’s conversion time simultaneously. An on-chip digital accumulator suitable for this sensor is also proposed. A prototype $1024 times 128$ CMOS TDI image sensor is fabricated in the 0.18- $mu text{m}$ CMOS technology, and the measurement results proof that the pixels and readout circuits in the sensor work properly. With a line rate of 3875 lines/s, the sensor costs a power consumption of 290 mW and a silicon area of $18.2~textrm {mm}times 18.9$ mm. The estimated maximum sensitivity of the fabricated sensor is 2010 $textrm {V}/textrm {lux}cdot textrm {sec}$ . This paper is suitable for applications in low-illumination, high scanning speed, and remote sensing systems." @default.
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- W2276093224 date "2016-03-01" @default.
- W2276093224 modified "2023-10-03" @default.
- W2276093224 title "A 128-Stage CMOS TDI Image Sensor With On-Chip Digital Accumulator" @default.
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- W2276093224 doi "https://doi.org/10.1109/jsen.2015.2499743" @default.
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