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- W2281272409 abstract "In recent years, researchers have explored use of non-volatile devices such as STT-RAM (spin torque transfer RAM) for designing on-chip caches, since they provide high density and consume low leakage power. A common limitation of all non-volatile devices is their limited write endurance. Further, since existing cache management policies are write-variation unaware, excessive writes to a few blocks may lead to a quick failure of the whole cache. We propose an architectural technique for wear-leveling of non-volatile last level caches (LLCs). Our technique uses cache-coloring approach which adds a software-controlled mapping layer between groups of physical pages and cache sets. Periodically the mapping is altered to ensure that write-traffic can be spread uniformly to different sets of the cache to achieve wear-leveling. Simulations performed with an x86-64 simulator and SPEC2006 benchmarks show that our technique reduces the worst-case writes to cache blocks and thus improves the cache lifetime by 4.07X." @default.
- W2281272409 created "2016-06-24" @default.
- W2281272409 creator A5012290807 @default.
- W2281272409 date "2013-10-31" @default.
- W2281272409 modified "2023-09-27" @default.
- W2281272409 title "Using Cache-coloring to Mitigate Inter-set Write Variation in Non-volatile Caches." @default.
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