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- W2281296338 abstract "A network is a high-level description of a digital circuit; the basic processing elements are abstracted as Each cell realizes a given function, and cells can be either normal or faulty. In a faulty cell, the function realized normally by it is altered in an arbitrary way. A procedure is presented for deriving fault detection test sets for combinational networks under the assumption that any number of cells can be faulty. It is based on the idea of decomposing the network into smaller subnetworks and testing them one by one. Of course, while testing a particular subnetwork, the rest of the network interferes in an unknown way, since it may contain faulty cells. This is taken care of by choosing suitable subnetworks that are used as observers of the values on some properly chosen internal lines. Conditions on the cell functions of the fault-free network are given that guarantee the existence of small test sets. The procedure is applied to derive linear-size test sets for two important networks, the Array Multiplier and the Unary-to-Binary Converter. Also, one- and two-dimensional orthogonally connected arrays are examined; conditions on the cell functions are given that guarantee the existence of a linear-size test set." @default.
- W2281296338 created "2016-06-24" @default.
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- W2281296338 date "1984-01-01" @default.
- W2281296338 modified "2023-09-23" @default.
- W2281296338 title "Multiple fault detection in digital circuits" @default.
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