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- W2283375425 abstract "This paper presents a 1.9-GHz digital ΔΣ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in 0.11-μm CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region." @default.
- W2283375425 created "2016-06-24" @default.
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- W2283375425 date "2015-06-30" @default.
- W2283375425 modified "2023-09-26" @default.
- W2283375425 title "An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL" @default.
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- W2283375425 doi "https://doi.org/10.5573/jsts.2015.15.3.342" @default.
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