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- W2285361507 abstract "In this chapter, the silicon-on-insulator (SOI) silicide technologies are described starting from the review of silicide design analysis on SOI, including the effects of source/drain series resistance and gate resistance on SOI device performance, the silicide thickness design analysis, and silicon resistivity design space for a specific design constraint. The dominant parameters for silicidation on SOI devices are the silicide/Si specific contact resistivity, the silicide thickness, and the silicon resistivity. Both the interface-specific contact resistivity and the silicon resistivity are directly related to the dopant concentration in the silicon layer. To minimise these resistivities, the degenerate doping in the source/drain regions is needed to be minimised to the order of 1020 cm-3. The challenges to implement existing bulk silicide technology to SOI devices are introduced which include titanium silicide process and voids, silicide thickness control, and thin silicide thermal stability. Finally, various silicide technologies on SOI including pre-amorphisation source/drain regions to control silicide depth, cobalt and nickel silicide technology for thin film SOI devices, low-barrier silicides of ErSi2 and PtSi for sub-20 nm novel devices, as well as selective silicide deposition on SOI, are discussed." @default.
- W2285361507 created "2016-06-24" @default.
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- W2285361507 date "2011-10-06" @default.
- W2285361507 modified "2023-09-26" @default.
- W2285361507 title "Silicide technology for SOI devices" @default.
- W2285361507 doi "https://doi.org/10.1049/pbep005e_ch8" @default.
- W2285361507 hasPublicationYear "2011" @default.
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