FRINK Linked Data Fragments server

Matches in SemOpenAlex for { <https://semopenalex.org/work/W2293076534> ?p ?o ?g. }

• W2293076534 abstract "With the rapid advances in VLSI process technology, layout synthesis is becoming increasingly complex. Parallel processing is fast becoming an attractive solution to reduce the inordinate amount of time spent in VLSI circuit design. In this thesis, we investigate algorithms and their parallel implementations for module placement, global routing for standard cells, and layout synthesis for clock trees.Using the matrix perturbation approach, we present a fast and effective module placement algorithm which is based on the PROUD algorithm. The new modified PROUD algorithm performs significantly faster than the original PROUD algorithm. We subsequently propose a parallel version of the modified algorithm that combines both fine grain and coarse grain parallelism to obtain another order of magnitude improvement in the runtime with very little loss of the quality of the layout.We propose three different parallel algorithms based on a state-of-the-art global router for area-minimization called TimberWolf 6.0. The first algorithm partitions the pins in a row-wise manner among the processors. The second algorithm partitions the nets and their corresponding pins among the processors. The third algorithm uses a hybrid approach. Both pin row partitioned algorithm and hybrid pin partitioned algorithms provide good speedup and quality.By integrating high performance interconnection tree construction, wire-sizing, and switchable segment channel optimization together, we propose an adaptive timing-driven global routing algorithm which minimizes the timing delay as well as circuit area. In addition, we proposed a parallel algorithm to reduce the excessive running time of our timing-driven global router, which is the first work on parallel timing-driven global routing.We propose two algorithms to get the exact zero skew wire-sizing for clock tree routing. Our experiments on benchmark clock trees show that one of the algorithms reduces the source sink delay significantly that of the clock trees with uniform wire sizes and keeps the clock skew zero. We also propose a parallel algorithm using a cluster-based clock tree construction algorithm and our zero skew wire-sizing algorithm.Using the Message Passing Interface (MPI), all of our parallel algorithm were implemented on various multiprocessor systems for a variety of large layout benchmark circuits." @default.
• W2293076534 created "2016-06-24" @default.
• W2293076534 creator A5028529662 @default.
• W2293076534 creator A5041622284 @default.
• W2293076534 date "1997-01-01" @default.
• W2293076534 modified "2023-09-27" @default.
• W2293076534 title "Novel algorithms for placement and routing and their parallel implementations" @default.
• W2293076534 cites W1485193993 @default.
• W2293076534 cites W1507707340 @default.
• W2293076534 cites W1533469848 @default.
• W2293076534 cites W1544310393 @default.
• W2293076534 cites W1565934040 @default.
• W2293076534 cites W1578824783 @default.
• W2293076534 cites W1857790976 @default.
• W2293076534 cites W189837128 @default.
• W2293076534 cites W1976156763 @default.
• W2293076534 cites W1979569488 @default.
• W2293076534 cites W1986024870 @default.
• W2293076534 cites W2008950155 @default.
• W2293076534 cites W2010948284 @default.
• W2293076534 cites W2023981464 @default.
• W2293076534 cites W2031904783 @default.
• W2293076534 cites W2040630985 @default.
• W2293076534 cites W2044944864 @default.
• W2293076534 cites W2062052521 @default.
• W2293076534 cites W2068670364 @default.
• W2293076534 cites W2072974175 @default.
• W2293076534 cites W2081628699 @default.
• W2293076534 cites W2087275089 @default.
• W2293076534 cites W2109319207 @default.
• W2293076534 cites W2117492357 @default.
• W2293076534 cites W2119842417 @default.
• W2293076534 cites W2120985183 @default.
• W2293076534 cites W2123586523 @default.
• W2293076534 cites W2124750239 @default.
• W2293076534 cites W2136768070 @default.
• W2293076534 cites W2143827795 @default.
• W2293076534 cites W2149671728 @default.
• W2293076534 cites W2149698600 @default.
• W2293076534 cites W2150609234 @default.
• W2293076534 cites W2153580689 @default.
• W2293076534 cites W2162122092 @default.
• W2293076534 cites W2163996522 @default.
• W2293076534 cites W2167421626 @default.
• W2293076534 cites W2169347255 @default.
• W2293076534 cites W2293958994 @default.
• W2293076534 cites W3138807513 @default.
• W2293076534 hasPublicationYear "1997" @default.
• W2293076534 type Work @default.
• W2293076534 sameAs 2293076534 @default.
• W2293076534 citedByCount "0" @default.
• W2293076534 crossrefType "journal-article" @default.
• W2293076534 hasAuthorship W2293076534A5028529662 @default.
• W2293076534 hasAuthorship W2293076534A5041622284 @default.
• W2293076534 hasConcept C11413529 @default.
• W2293076534 hasConcept C117690923 @default.
• W2293076534 hasConcept C120373497 @default.
• W2293076534 hasConcept C127879752 @default.
• W2293076534 hasConcept C14580979 @default.
• W2293076534 hasConcept C149635348 @default.
• W2293076534 hasConcept C173608175 @default.
• W2293076534 hasConcept C188817802 @default.
• W2293076534 hasConcept C190560348 @default.
• W2293076534 hasConcept C2775896111 @default.
• W2293076534 hasConcept C31258907 @default.
• W2293076534 hasConcept C41008148 @default.
• W2293076534 hasConcept C68339613 @default.
• W2293076534 hasConcept C74172769 @default.
• W2293076534 hasConceptScore W2293076534C11413529 @default.
• W2293076534 hasConceptScore W2293076534C117690923 @default.
• W2293076534 hasConceptScore W2293076534C120373497 @default.
• W2293076534 hasConceptScore W2293076534C127879752 @default.
• W2293076534 hasConceptScore W2293076534C14580979 @default.
• W2293076534 hasConceptScore W2293076534C149635348 @default.
• W2293076534 hasConceptScore W2293076534C173608175 @default.
• W2293076534 hasConceptScore W2293076534C188817802 @default.
• W2293076534 hasConceptScore W2293076534C190560348 @default.
• W2293076534 hasConceptScore W2293076534C2775896111 @default.
• W2293076534 hasConceptScore W2293076534C31258907 @default.
• W2293076534 hasConceptScore W2293076534C41008148 @default.
• W2293076534 hasConceptScore W2293076534C68339613 @default.
• W2293076534 hasConceptScore W2293076534C74172769 @default.
• W2293076534 hasLocation W22930765341 @default.
• W2293076534 hasOpenAccess W2293076534 @default.
• W2293076534 hasPrimaryLocation W22930765341 @default.
• W2293076534 hasRelatedWork W109722725 @default.
• W2293076534 hasRelatedWork W1983950263 @default.
• W2293076534 hasRelatedWork W1990633131 @default.
• W2293076534 hasRelatedWork W2033449073 @default.
• W2293076534 hasRelatedWork W2038339975 @default.
• W2293076534 hasRelatedWork W2053295722 @default.
• W2293076534 hasRelatedWork W2077903996 @default.
• W2293076534 hasRelatedWork W2101374297 @default.
• W2293076534 hasRelatedWork W2120297219 @default.
• W2293076534 hasRelatedWork W2123118545 @default.
• W2293076534 hasRelatedWork W2125692303 @default.
• W2293076534 hasRelatedWork W2132957413 @default.
• W2293076534 hasRelatedWork W2147187626 @default.
• W2293076534 hasRelatedWork W2293605855 @default.
• W2293076534 hasRelatedWork W2760693421 @default.

• next