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• W2293864981 abstract "The Strongly Connected Components (SCCs) detection algorithm serves as a keystone for many graph analysis applications. The SCC execution time for large-scale graphs, as with many other graph algorithms, is dominated by memory latency. In this article, we investigate the design of a parallel hardware architecture for the detection of SCCs in directed graphs. We propose a design methodology that alleviates memory latency and problems with irregular memory access. The design is composed of 16 processing elements dedicated to parallel Breadth-First Search (BFS) and eight processing elements dedicated to finding intersection in parallel. Processing elements are organized to reuse resources and utilize memory bandwidth efficiently. We demonstrate a prototype of our design using the Convey HC-2 system, a commercial high-performance reconfigurable computing coprocessor. Our experimental results show a speedup of as much as 17× for detecting SCCs in large-scale graphs when compared to a conventional sequential software implementation." @default.
• W2293864981 created "2016-06-24" @default.
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• W2293864981 date "2015-12-04" @default.
• W2293864981 modified "2023-10-14" @default.
• W2293864981 title "A Reconfigurable Architecture for the Detection of Strongly Connected Components" @default.
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• W2293864981 doi "https://doi.org/10.1145/2807700" @default.
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