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• W2296094894 abstract "Key markets, such as automotive, wearables, and internet-of-things (IoT) are spearheading the drive to realize more sophisticated packaging technologies that include the growing use of interposers and 3D ICs. With the goal of improving processing performance, increasing clock speeds, and reducing power consumption, design teams are challenged with ensuring signal quality, power delivery, and thermal behavior are within specification for target applications. During the design process, engineers must access many design and analysis tools, though most of the design flow is often disconnected and design data is exchanged manually. The existing approach results in an error-prone process and increases the overall design cycle time. With a traditional approach, design teams are typically expected to take on 3D problems using 2D tools. To help address these challenges, we will look at how a 3D systemlevel co-design with multi-physics analysis approach helps overcome common obstacles for an automotive application for a CPU design. This case study explores the thermal impact of stacking multiple chips using through silicon vias (TSVs) on a four-layer substrate placed on a printed circuit board (PCB). The new methodology highlights how to overcome hurdles during the design process and how it enables the design team to work together more effectively using a co-design approach when multiple chips, packages, and PCBs are assembled together as a product. This case study also reviews instances where engineers are only able to detect performance issues late in the design process or even after the design is completed. For applications used in automotive and other markets, the chips used in the case study also include packages with high pin count densities. With so many vertical elements, such as vias, TSVs, controlled collapse chip connection (C4) bumps and micro-bumps, conducting simulation and analysis can exponentially increase time to derive accurate results. To utilize 3D full-wave field solvers, the objects within these advanced packages have to be meshed as part of the analysis process, and that increases the overall time to model and process the simulation results. Through this new methodology, we will review best practices for managing objects and shapes within the design to help reduce the computation time to generate results faster with minimal effect to the accuracy for signal/power integrity and thermal analyses." @default.
• W2296094894 created "2016-06-24" @default.
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• W2296094894 date "2016-01-01" @default.
• W2296094894 modified "2023-09-24" @default.
• W2296094894 title "Improving design performance with system-level co-design and multi-physics analysis: Thermal and stress-aware design for three dimensional stacked IC package" @default.
• W2296094894 doi "https://doi.org/10.1109/panpacific.2016.7428396" @default.
• W2296094894 hasPublicationYear "2016" @default.
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