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• W2296730406 abstract "Stencil computations are at the core of applications in a number of scientific computing domains. We describe a domain-specific language for regular stencil computations that allows specification of the computations in a concise manner. We describe a multi-target compiler for this DSL, which generates optimized code for GPUa, FPGAs, and multi-core processors with short-vector SIMD instruction sets, considering both low-order and high-order stencil computations. The hardware differences between these three types of architecture prompt different optimization strategies for the compiler. We evaluate the domain-specific compiler using a number of benchmarks on CPU, GPU and FPGA platforms." @default.
• W2296730406 created "2016-06-24" @default.
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• W2296730406 date "2015-11-15" @default.
• W2296730406 modified "2023-10-16" @default.
• W2296730406 title "SDSLc" @default.
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• W2296730406 doi "https://doi.org/10.1145/2830018.2830025" @default.
• W2296730406 hasPublicationYear "2015" @default.
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