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- W2299607564 abstract "Approaches to design fault tolerant Network-on-Chip (NoC) for System-on-Chip(SoC)-based reconfigurable Field-Programmable Gate Array (FPGA) technology are challenges on the conceptualisation of the Multiprocessor System-on-Chip (MPSoC) design. For this purpose, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in a validation architecture. The Event-B formal method is a promising formal approach that can be used to develop, model and prove accurately the domain of SoCs and MPSoCs. This paper gives a formal verification of a NoC architecture, using the Event-B methodology. The formalisation process is based on an incremental and validated correct-by-construction development of the NoC architecture." @default.
- W2299607564 created "2016-06-24" @default.
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- W2299607564 date "2012-12-16" @default.
- W2299607564 modified "2023-10-15" @default.
- W2299607564 title "Formal Verification of Fault Tolerant NoC-based Architecture" @default.
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