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- W2300812672 abstract "As part of its initiative to have application specific integrated circuits (ASICs) adopted as relevant technology by the New Zealand electronics industry, the Physics and Engineering Laboratory has designed its own gate array database using its in-house 5 micron n-well silicon gate CMOS process. Although a low complexity gate array, it can still replace several conventional integrated circuits in a design and provide a low cost entry to ASIC design for New Zealand without the problem of remote access incurred when operating with overseas vendors. In addition, the circuit design has been simplified for the user by a personal computer CAD package developed by Wellington Polytechnic and made available at a nominal cost. The paper discusses the design of the database, development of library cells, experiences in the fabrication of the database, the development of the CAD package, a circuit design for the gate array, development of test structures and a testing strategy, actual testing and final characterisation of the gate array. Conclusions are drawn based on experiences gained from the exercise, the merit of the gate array given current technology is debated and future plans are described." @default.
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- W2300812672 date "1989-01-01" @default.
- W2300812672 modified "2023-09-23" @default.
- W2300812672 title "A Low Complexity Gate Array for the New Zealand Situation" @default.
- W2300812672 hasPublicationYear "1989" @default.
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