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• W2303722505 abstract "Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual $V_{mathrm {ref}}$ sensing scheme (DVSS) that selectively uses an optimal $V_{rm {ref}}$ between $V_{rm {ref+}}$ and $V_{rm {ref-}}$ is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal $V_{rm {ref}}$ is selected after fabrication, and the calibrated switch control bit, which contains $V_{{rm {ref}}}$ selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with $2times $ faster sensing speed and $1.5times $ lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme." @default.
• W2303722505 created "2016-06-24" @default.
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• W2303722505 date "2016-04-01" @default.
• W2303722505 modified "2023-09-27" @default.
• W2303722505 title "An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM" @default.
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• W2303722505 doi "https://doi.org/10.1109/tvlsi.2015.2453192" @default.
• W2303722505 hasPublicationYear "2016" @default.
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