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- W2309221519 abstract "An energy-efficient single bit full adder based on energy recovery CMOS XOR/XNOR using Clocked Adiabatic Logic (CAL), 2N-2N2P and transmission gate multiplexer has been presented in 0.35 μm technology. The adder using CAL (20T) XNOR/XOR and multiplexer-based architecture gives a power dissipation of 661.2466 μW, whereas the architecture based on CAL (18T) dissipates 661.315 μW. Further, the adder designed with 2N-2N2P (16T) XNOR/XOR and multiplexer approach dissipates minimum power of 642.4407 μW. Moreover, the effect of gate length of transistor has also been considered for the evaluation of power dissipation. By varying the gate length of the transistor from 0.35 μm to 1 μm, an improvement of 63.25%, 67.91% and 2.56% in power consumption has been achieved using CAL (20T) XNOR/XOR, CAL (18T) XNOR/XOR and 2N-2N2P (16T) respectively." @default.
- W2309221519 created "2016-06-24" @default.
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- W2309221519 date "2011-01-01" @default.
- W2309221519 modified "2023-09-23" @default.
- W2309221519 title "An Energy-Efficient Full Adder Design Based on Energy Recovery Gates and Multiplexer Architecture" @default.
- W2309221519 hasPublicationYear "2011" @default.
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