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• W2310366333 abstract "This paper presents the implementation of a 17 bits digital pulse width modulator (DPWM). Smaller pulses were obtained using internal carry chains that are available in many FPGAs. Our proposed architecture minimizes the critical paths that influence the linearity and induces the creation of carry chains without the use of adders. The frequency of the DPWM is 90.5kHz with a resolution of approximately 80ps, and the clock frequency is 46.34MHz." @default.
• W2310366333 created "2016-06-24" @default.
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• W2310366333 date "2015-12-01" @default.
• W2310366333 modified "2023-09-26" @default.
• W2310366333 title "Implementation of a 17 bits Pulse Width Modulation circuit using FPGA" @default.
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• W2310366333 doi "https://doi.org/10.1109/icm.2015.7438024" @default.
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