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- W2312384561 abstract "Logic depth aware static timing analysis involves a pre-characterized library that models the variability over the path on the basis of total timing path depth. With shrinking design geometries and rush to pack more components in a reduced size chip, hierarchical timing analysis has emerged as a stronger alternative to closing the designs however logic depth based timing analysis brings new set of challenges in generating timing models for the multiply instantiated hierarchical blocks at the chip level. In this paper, we discuss challenges imposed by logic depth in creating hierarchical timing analysis and propose a new algorithm in generating a model comprehending logic depths for multiply instantiated blocks. We demonstrate that usage of such timing model generation algorithm can significantly speedup the process of model extraction and process accuracy within 10% of the original block timing." @default.
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- W2312384561 date "2016-01-01" @default.
- W2312384561 modified "2023-09-25" @default.
- W2312384561 title "Logic depth aware context independent timing model generation" @default.
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- W2312384561 doi "https://doi.org/10.1063/1.4942704" @default.
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