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- W2313740073 abstract "A hardware-efficient method of the poly-phase filter bank is introduced in this paper, and a filter bank with 16-fold decimation factor and 32 data paths based on the FPGA is presented. The Single-MAC FIR filters and the IFFT module based on the switch-cascade architecture are used in this design, a fact which can improve the system clock frequency and also shrink hardware logic resources greatly. The result indicated that the method is a high-efficient and the lowest cost for hardware implementation of the filter bank." @default.
- W2313740073 created "2016-06-24" @default.
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- W2313740073 date "2015-01-01" @default.
- W2313740073 modified "2023-10-08" @default.
- W2313740073 title "Efficient implementation of the filter bank based on FPGA" @default.
- W2313740073 doi "https://doi.org/10.1049/cp.2015.0207" @default.
- W2313740073 hasPublicationYear "2015" @default.
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