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- W2321782868 abstract "A 64-kbit, low power MOS RAM, composed of 2µm channel MOS transistors, has been developed. At first, analysis with sense circuit was made and the relation between sensitivity and factors which affect sensitivity was clarified. According to the guide lines obtained from the relation, development of a new sense circuit and design method for the sense circuit were made. It has been verified that the sense circuit can detect a signal smaller than ±30 mV through the fabrication of a 1K RAM. A new level detecting circuit, having a logic threshold voltage independent of MOS transistor threshold voltage, has been developed. The circuit gives a large margin to TTL interface circuits in LSI. The 64K characteristics are 200 ns access time, 500 ns cycle time and 150 mW power consumption under typical voltage conditions; 7V (VDD) and -2V (VBB)." @default.
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- W2321782868 date "1978-01-01" @default.
- W2321782868 modified "2023-09-25" @default.
- W2321782868 title "(Invited) A 64K MOS RAM Design" @default.
- W2321782868 doi "https://doi.org/10.7567/jjaps.17s1.57" @default.
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