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- W2324955515 abstract "System-on-a-Chip (SoC) design has become more and more complexly. How to verify a design effectively has become a serious challenge. In this paper, how to build up the effective verification environment of AXI using SystemVerilog is introduced. Firstly, the design under verify (DUV) AXI bus is introduced. Then a comprehensive analysis of the verification plan has been made according to the protocol. The proposed integrated verification environment with Functional coverage, score-boarding, assertions and constrained random vectors generation is implemented. With this environment, a high coverage and less time spending verification has been achieved. " @default.
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- W2324955515 date "2013-01-01" @default.
- W2324955515 modified "2023-09-23" @default.
- W2324955515 title "Development of Verification Environment for AXI Bus Using SystemVerilog" @default.
- W2324955515 cites W2125597111 @default.
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- W2324955515 doi "https://doi.org/10.12720/ijeee.1.2.112-114" @default.
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