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- W2328219794 abstract "Regular expression matching is a computational intensive task, used in applications such as intrusion detection and DNA sequence analysis. Many hardware-based regular expression matching architectures are proposed for high performance matching. In particular, regular expression matching processors such as ReCPU have been proposed to solve the problem that full hardware solutions require re-synthesis of hardware whenever the patterns are updated. However, ReCPU has inefficient failure processing due to data backtracking. In this paper, we propose an efficient failure processing architecture for regular expression processor. The proposed architecture uses the failure bit included in instruction format and provides efficient failure processing by removing unnecessary data backtracking." @default.
- W2328219794 created "2016-06-24" @default.
- W2328219794 creator A5091137700 @default.
- W2328219794 date "2015-06-13" @default.
- W2328219794 modified "2023-09-26" @default.
- W2328219794 title "Efficient Failure Processing Architecture in Regular Expression Processor" @default.
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- W2328219794 doi "https://doi.org/10.5121/csit.2015.51201" @default.
- W2328219794 hasPublicationYear "2015" @default.
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