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- W2330397072 abstract "Evolvable hardware is a new method for designing the digital logic circuits. In this paper, a method has been presented for designing the synchronous sequential logic circuit by using the evolvable hardware. In this approach, the sequential logic circuit is divided into two sections; the combinational logic circuit and DFFs. The combinational logic part is designed by using a constant structure and their connections are set with genetic algorithm (GA). The results show that our method can reduce the average number of generations by limitation the search space." @default.
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- W2330397072 date "2012-01-01" @default.
- W2330397072 modified "2023-09-26" @default.
- W2330397072 title "Improvement of Optimization in Design of Synchronous Sequential Circuits by Using Evolvable Hardware" @default.
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- W2330397072 doi "https://doi.org/10.7763/ijcte.2012.v4.584" @default.
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