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• W2334204162 abstract "Cryptographic S-boxes are fundamental in key-iterated substitution permutation network (SPN) designs for block ciphers. As a natural way for realizing Shannon’s confusion and diffusion properties in cryptographic primitives through nonlinear and linear behavior, respectively, SPN designs served as the basis for the Advanced Encryption Standard and a variety of other block ciphers. In this work we present a methodology for minimizing the logic resources for n-bit affine-power Sboxes over Galois fields based on measurable security properties and finding corresponding area-efficient combinational implementations in hardware. Motivated by the potential need for new and larger S-boxes, we use our methodology to find area-optimized circuits for 8and 16-bit S-boxes. Our methodology is capable of finding good upper bounds on the number of XOR and AND gate equivalents needed for these circuits, which can be further optimized using modern CAD tools." @default.
• W2334204162 created "2016-06-24" @default.
• W2334204162 creator A5059586610 @default.
• W2334204162 creator A5071708090 @default.
• W2334204162 creator A5075568055 @default.
• W2334204162 date "2015-01-01" @default.
• W2334204162 modified "2023-09-27" @default.
• W2334204162 title "Affine-Power S-Boxes over Galois Fields with Area-Optimized Logic Implementations" @default.
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• W2334204162 hasPublicationYear "2015" @default.
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