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- W2334429401 abstract "The path to Exascale performance is likely to be based on CPU chips with multiple processor cores per die, direct attached memory, and thousands of nodes connected together in a high bandwidth, distributed memory network. This talk will focus on the micro architectural challenges in such a system: How we can minimize power consumption, design an effective local memory system, and access remote memory with a high bandwidth, low latency network. We consider emerging 3D packaging technologies, on die interconnects, the role of cache coherence domains, and CPU-Network interface functionality." @default.
- W2334429401 created "2016-06-24" @default.
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- W2334429401 date "2014-09-07" @default.
- W2334429401 modified "2023-09-23" @default.
- W2334429401 title "Computer Architecture for Exascale" @default.
- W2334429401 doi "https://doi.org/10.3997/2214-4609.20141924" @default.
- W2334429401 hasPublicationYear "2014" @default.
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