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• W2336675781 abstract "Designing memory systems for high-throughput computing has always been a challenging task one that is getting even harder with increasing bandwidth requirements and increasing application complexity. Simply relying on traditional memories alone is not likely to be scalable or cost effective. While Ternary CAM (TCAM) provides high throughput with very simple worst-case analysis, it can consume large amount of power. On the other hand, SRAM requires very careful worst-case analysis and is limited in overall bandwidth, limited by on-chip capacity, and is not immune from power consumption issues either. DRAMs can deliver a great deal of throughput, but the problem is that memory banking significantly complicates the worst-case analysis, and specialized algorithms are needed to ensure that specific types of access patterns are conflict free. In this thesis, we propose novel design methods that cut across the traditional boundaries of circuits, architecture, and algorithms that when applied to traditional memories address the following problems: (1) Early design estimation for on-chip SRAM (2) Power management in TCAM, (3) Bank conflicts in DRAM, and (4) Bandwidth and capacity limitations in on-chip SRAM. First, to perform an early design estimation for on-chip memories, we build our model using the characterization of almost 60 real memory designs from the past 15 years. Our model, along with the presented methodology, can be used to calibrate even more detailed memory models for better accuracy. Second, researchers at all levels of design (from algorithms to circuits) have begun to explore new ways to manage the power consumption in TCAM. However, quantifying design alternatives is difficult due to a lack of available models. Therefore, we present a simple, yet accurate, power and delay model by examining the internal structure of TCAM. Such a model is a critical first step in bridging the intellectual divide between circuit-level and algorithm-level optimizations. Third, to attack the problems of bank conflicts in DRAM, we present a virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high throughput even under adversarial conditions. We present a mathematical argument for our system's ability to provably provide bandwidth with high confidence. Finally, to provide high-bandwidth on-chip memory, we extend the technique of virtual pipelining to be applicable for on-chip DRAM, which can then replace the traditional role of fast SRAM in network algorithm design. By solving all these challenges, we enable practical memory design options for both on-chip and off-chip memory in the domain of high throughput computing." @default.
• W2336675781 created "2016-06-24" @default.
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• W2336675781 date "2008-01-01" @default.
• W2336675781 modified "2023-09-27" @default.
• W2336675781 title "Memory modeling and design for high throughput computing" @default.
• W2336675781 hasPublicationYear "2008" @default.
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