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- W2341039022 abstract "D numerical simulation of normally off vertical N- channel JFET with novel internal lateral gate configuration designed on a 9.4 μm, 7 × 1015 cm−3 doped drift layer is presented. The study covers an interval of blocking voltages ranging from 600 V to 933 V for various temperatures and channel widths. The effect of elimination of vertical JFET gates and variation in channel width on the on-state/breakdown performance is carefully investigated. The device performance has been compared in terms of blocking voltages, specific on- state resistance and maximum output current density in the temperature range from room temperature up to 473 K. Normally-off operation with blocking voltage (Vbl) of 933 V is demonstrated for a gate voltage of -20 V. The goal of this work is to predict the performance of lateral gate VJFET configuration and have a deep insight into the relationship between the device's electrical/thermal characteristics and channel thickness. The detailed investigation reveals that lateral gate configuration offers less resistance to leakage current reducing the blocking capability of the device. Though, it's excellent on state performance in terms of high saturation current (1.23A) and low on-resistance (3.6 m Ω) makes this VJFET an excellent device for fast power switching applications." @default.
- W2341039022 created "2016-06-24" @default.
- W2341039022 creator A5025578352 @default.
- W2341039022 date "2016-04-08" @default.
- W2341039022 modified "2023-09-25" @default.
- W2341039022 title "Temperature and Channel width Dependence of Novel Lateral Gate VJFET" @default.
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- W2341039022 doi "https://doi.org/10.5281/zenodo.49365" @default.
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