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• W2342255478 abstract "This paper presents the FPGA implementation of a Decimal Floating Point (DFP) arithmetic unit. The design performs addition, subtraction and multiplication on 64-bit operands that use the IEEE 754-2008 DPD encoding of DFP numbers. The design uses an equal bypass adder, this adder reduces the power consumption and it also reduces the delay by reducing the gate count. The design also uses barrel shifter instead of sequential shifter to reduce delay. Also 64 bit parallel BCD multiplier is used to perform fixed point multiplication. The proposed DFP arithmetic unit supports operations on the decimal64 format and it is easily extendable for the decimal128 format." @default.
• W2342255478 created "2016-06-24" @default.
• W2342255478 creator A5043245464 @default.
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• W2342255478 date "2015-12-26" @default.
• W2342255478 modified "2023-09-28" @default.
• W2342255478 title "Implementation of Optimized Floating Point Arithmetic Unit on Reconfigurable Logic" @default.
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• W2342255478 doi "https://doi.org/10.32628/ijsrset151678" @default.
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