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- W2347272589 abstract "Firstly,the BCH codes used in DTMB system is a cyclic Hamming code is proved,whose correction capability is one bit.According to this,a decoding algorithm of the BCH codes is proposed.Then a serial decoder and a parallel decoder based on FPGA are designed.Taking into account the characteristics of the shorten BCH codes,the decoding delay of them is reduced by 34%.The implementation results show that the decoders decode correctly and consume very little FPGA resources.The total delay of the serial decoder is 762 clock cycles,and the maximum clock frequency of that can reach 357 MHz.While the total delay of the parallel decoder is only 77 clock cycles and the maximum clock frequency of that can reach 276 MHz." @default.
- W2347272589 created "2016-06-24" @default.
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- W2347272589 date "2013-01-01" @default.
- W2347272589 modified "2023-09-24" @default.
- W2347272589 title "Decoding Algorithm and FPGA Implementation of BCH Codes in DTMB" @default.
- W2347272589 hasPublicationYear "2013" @default.
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