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- W2347351637 abstract "Programmable Logic Cells (LCs) play an important role in Field Programmable Gate Array (FPGA). Its performance will influence the whole performance of FPGA. So LC and the design method of its architecture is the important content in FPGA research. In this paper, n-input Look-Up Table (n-LUT) is expanded to be an Extended LUT (ELUT) by Shannon formula. The ELUT can not only implement all n-input functions, but also realize partial (n+1)～(2n-1) input functions. Thus the capacity of implementing function is enhanced under the condition of not increasing MOS transistor. By these characteristics, one 3-LUT is expanded to be 7-ELUT by Shannon formula. Then an ELUT-based LC architecture is presented by function enhancement and optimization based on one-bit Full Adder (FA) including adding fast carry chain, special cascade chain, and so on. The ELUT-based LC can not only implements arbitrary 3-input and partial 7-input function, but also realizes fast arithmetic and high fan input logic function. The LC is consists of the ELUT-based combination logic, sequence logic, cascade logic, etc. Besides general combination logic, the LCs can also implement fast datapath application logics availably such as fast full adder, multiplier, shifter and so on with fast carry chains. In additional, two cascade logics in the LC can support fast high fan logic function effectively so as to support implementing general combination logic and Finite State Machine (FSM) well. By compared with existing commercial FPGA, the LC occupies little chip area and is less MOS transistors. FPGA, be made up of the LC, can economize 40% MOS transistors compared with commercial FPGA when some important logic including datapath application logics are implemented. And one of the LCs is less than a 4-LUT too. Otherwise, the LC has favorable expansibility, regular architecture, and can be mapped easily with CAD tools. The experiments show that the LC architecture has excellent capacity of implementing function, and fast logic speed." @default.
- W2347351637 created "2016-06-24" @default.
- W2347351637 creator A5021610566 @default.
- W2347351637 date "2003-01-01" @default.
- W2347351637 modified "2023-09-25" @default.
- W2347351637 title "An ELUT-Based Programmable Logic Cell" @default.
- W2347351637 hasPublicationYear "2003" @default.
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