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- W2350010583 abstract "SoC is a VLSI with microprocessor,peripheral circuits,and so on. SoC has some special features such as small device feature size,unusual complexity,large chip size and mixed-signals,etc.. All this leads chip designer to a new challenge in SoC ESD design. A whole-chip ESD protection solution of complicated multipower,mixed-voltage,application-specified SoC is proposed in this paper. Considering the chip specialties,detailed analyses for the ESD design difficulties of SoC are proposed in the paper. An analysis idea of process first,device then,circuit last for ESD design is provided. Detail analyses for design keys of ESD total solution are proposed one by one too. A whole-chip ESD protection composition of a picture is provided in the end. Based on 0.35μm 2P4M Polycide mixed-signal CMOS process,its HBM ESD level reaches 4kV by using the proposed whole-chip ESD protection plan." @default.
- W2350010583 created "2016-06-24" @default.
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- W2350010583 date "2009-01-01" @default.
- W2350010583 modified "2023-10-03" @default.
- W2350010583 title "The Whole-chip ESD Design for Multi-power and Mixed-voltage SoC" @default.
- W2350010583 hasPublicationYear "2009" @default.
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