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- W2353494116 abstract "The paper introduced the instruction buffer queue and the corresponding controller of a fixed-point digital signal processor YHFT-X,which with the character of the high performance and low power.In order to deliver the parallel instruction stream of high density and variable length,an improved dynamically-managed loop instruction buffer queue structure is designed,which has improved the technical limitations of looping instructions already existing.It impletation of the software pipelining operation by use the instruction buffer,greatly reduced the code volume,simplified the pipeline.It simultaneously lightens the pressure which brought to the memory by instruction fetch,reduced the power consumption,Supporting sub-block instruction prefetching techniques,which can eliminate partial unnecessary pipeline stall.Confirmation and contrastively test shows that this scheme is suitable for high-speed,low-power application finally." @default.
- W2353494116 created "2016-06-24" @default.
- W2353494116 creator A5011499594 @default.
- W2353494116 date "2010-01-01" @default.
- W2353494116 modified "2023-09-23" @default.
- W2353494116 title "Istruction Buffer Queue for High Performance and Low-power YHFT-XDSP" @default.
- W2353494116 hasPublicationYear "2010" @default.
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