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- W2355399521 abstract "It is the basic structure introuduced of DDR bus that is one product of the embedded.The interpretation of general rules is to meet so high-speed signal routing and signal integrity requirements.Then it combines with Allegro 15.2 which is dedicated high-speed PCB design,and overcomes the destruction of the main factors of reflection,crosstalk and so on.Through the use of serentine line,all signals remain a delay in a range,and guarantee the effective data of system in a cycle.According to this general rule for high-speed DDR cabling,wiring results meet the requirements of some high-speed situations." @default.
- W2355399521 created "2016-06-24" @default.
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- W2355399521 date "2011-01-01" @default.
- W2355399521 modified "2023-09-23" @default.
- W2355399521 title "Routing high-speed DDR Bus Research and Design" @default.
- W2355399521 hasPublicationYear "2011" @default.
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