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- W2359551405 abstract "This paper describes a reconfigurable array architecture based on pipelined loop computing.That is,the array processor communicates with the main processor through the AMBA interface.The paper introduces the architecture of PLAA especially 2D-DCT arithmetic implementation.The simulation results show that PLAA can achieve seven times or much higher performance than general processor,and make a balance among complexity,performance and compatibility." @default.
- W2359551405 created "2016-06-24" @default.
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- W2359551405 date "2010-01-01" @default.
- W2359551405 modified "2023-09-26" @default.
- W2359551405 title "A pipelined loop array architecture" @default.
- W2359551405 hasPublicationYear "2010" @default.
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