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- W2360693693 abstract "Dual fault-tolerant technique,a key technique to improve reliability of computer system,is widely applied in the design and development of embedded system.Based on various methods in common use and combined with correlative techniques of programmable devices,a scheme of the dual fault-tolerant system based on FPGA is presented.The arbitrator mechanism is important for the real implementation because it supervises the switches between the host and the backup machine.In the process of implementation,not only FPGA's inner resources were fully made use of,but also the circuit mistakes caused by signals' burrs were avoided using FPGA's inner clock signal to make the asynchronous signals synchronized.The simulational result shows good performance." @default.
- W2360693693 created "2016-06-24" @default.
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- W2360693693 date "2006-01-01" @default.
- W2360693693 modified "2023-09-23" @default.
- W2360693693 title "Design and implementation of the dual fault-tolerant system based on the FPGA" @default.
- W2360693693 hasPublicationYear "2006" @default.
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