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- W2361157664 abstract "A new approach was proposed to improve the overall performance of equivalence checking with complicate arithmetic circuits.The synthesis engine was made to replay the optimizations of arithmetic circuit.The algorithm combines the recognition technique of different coding methods in multiplier,the extraction technique of half adder graph(HAG) in addition circuit,and the recognition technique of half adder tree structure of partial product addition circuit.With the extracted information,the register transfer level(RTL) synthesis engine can generate a gate netlist that is logically correct and structurally similar to the implementation.Due to the similarity of arithmetic circuits,only the lower bits' outputs need analyz-ing,which decreases the algorithm complexity.Compared with the traditional verification algorithms of arithmetic circuits,the proposed algorithm can be easily incorporated into the existing RTL-gate equivalence checking frameworks and increase the robustness of the equivalence checking for arithmetic circuits,thus the verification performance is improved." @default.
- W2361157664 created "2016-06-24" @default.
- W2361157664 creator A5079925183 @default.
- W2361157664 date "2008-01-01" @default.
- W2361157664 modified "2023-09-23" @default.
- W2361157664 title "Combining half adder graph for equivalence checking of arithmetic circuits" @default.
- W2361157664 hasPublicationYear "2008" @default.
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