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- W2363720909 abstract "This paper presents the deskew function in Serdes Framer Interface Level 5(SFI-5) interface realized in an FPGA. The design is mainly consisted of the frame aligner of deskew channel and data channel deskew modules,the key part of which depends on the window comparison and a slip-window generator. 16 data channel deskew circuits works in turn and share one window comparison,improving the IC working speed and reducing circuit complexity greatly. Aon-system test is implemented in one Altera EP1SGX40GF1020C6 FPGA,with an Agilent 1682A logic analyzer. The test result indicates that the circuit can correct the skew between channels up to ±160 bits both reliably and steadily,which can be applied in actual 40Gb/s very short reach communication systems." @default.
- W2363720909 created "2016-06-24" @default.
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- W2363720909 date "2008-01-01" @default.
- W2363720909 modified "2023-09-23" @default.
- W2363720909 title "Deskew design in 40Gb/s very short reach optical transmission system" @default.
- W2363720909 hasPublicationYear "2008" @default.
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