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- W2364307072 abstract "As the NWPU AMEC's full copyright RISC microprocessor, LongtiumRR2 is compatible with PowerPC architecture. It is designed with six pipeline stages, the independent data cache and instruction cache. In this paper, we introduce the design and optimization of the pipelining, and focus on the elimination of pipelining hazard, the implementation of exact exception, the design and implementation of the instruction prefetching stage, etc." @default.
- W2364307072 created "2016-06-24" @default.
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- W2364307072 date "2006-01-01" @default.
- W2364307072 modified "2023-09-24" @default.
- W2364307072 title "Design and Optimization of the Pipeliningin RISCMicroprocessor Longtium~RR2" @default.
- W2364307072 hasPublicationYear "2006" @default.
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