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- W2364762005 abstract "Semiconductor manufacturing industry which is highly capital-intensive and complex manufacturing process is an important component of modern industry, and, assembly and test of chips are the very important processes of semiconductor manufacturing. In assembly and test department, the facility layout is Bay-Layout in which the department is formed of bays and same machines are located in one bay and WIP area is also located. So, for one bay, how to allocate the machines and WIP area to minimize the material handing cost and maximize the utilized rate of area are the optimal object of Bay-Layout, and in this paper, the optimal mathematic model of Bay-Layout is established and a new solving algorithm for this mathematic model is proposed." @default.
- W2364762005 created "2016-06-24" @default.
- W2364762005 creator A5072186094 @default.
- W2364762005 date "2009-01-01" @default.
- W2364762005 modified "2023-09-23" @default.
- W2364762005 title "The Researching of Algorithm for Bay-Layout in Semiconductor’s Assembly and Test Department" @default.
- W2364762005 hasPublicationYear "2009" @default.
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