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- W2366168864 abstract "Network processor is a specific processor optimized to network process,the instruction set is the interface between software and hardware,the design of instruction set can greatly influence processor performance.An optimized method to combine high frequency instruction pair to a new instruction is proposed in this paper,the method makes full use of the dynamic relativity in the execution of network processor benchmark,it exploits the unused bit in the instruction format of simplescalar to be the expansion field in the new instruction.Quantitative method is used to analyze the experimental result, the simulation result shows that the method can both improve the performance and decrease the I-cache power consumption,realize the tradeoff between performance and power consumption." @default.
- W2366168864 created "2016-06-24" @default.
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- W2366168864 date "2006-01-01" @default.
- W2366168864 modified "2023-09-23" @default.
- W2366168864 title "High Frequency Instruction Pair Combination and Analysis in Network Processor Design" @default.
- W2366168864 hasPublicationYear "2006" @default.
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