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- W2367704622 abstract "This paper presented a syntax checker for synthesizable subset of VHDL expressions to work out the difficulties brought by complex VHDL grammar, especially the flexibility of expressions. By changing grammar rules the checker eliminates the ambiguities of VHDL expressions. The expressions grammar rules and descriptions of test result were provided." @default.
- W2367704622 created "2016-06-24" @default.
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- W2367704622 date "2001-01-01" @default.
- W2367704622 modified "2023-09-25" @default.
- W2367704622 title "Syntax Checker for Synthesizable Subset of VHDL Expressions" @default.
- W2367704622 hasPublicationYear "2001" @default.
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